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Disambiguation of "Ikenaga, Takeshi"

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A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC.

, , , , and . J. Signal Process. Syst., 50 (1): 81-95 (2008)

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Takeshi Morita

Mamiko Ikenaga

Takeshi Morita

Takeshi Imamura

Takeshi Omori

 

Other publications of authors with the same name

A parallel LSI architecture for LDPC decoder improving message-passing schedule., , , , and . ISCAS, IEEE, (2006)A locally adaptive subsampling algorithm for software based motion estimation., , , and . ISCAS (3), page 2891-2894. IEEE, (2005)Smart feature detection device for cloud based video recognition system., and . VLSI-DAT, page 1-3. IEEE, (2014)FPGA implementation of high frame rate and ultra-low delay vision system with local and global parallel based matching., and . MVA, page 286-289. IEEE, (2017)32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application., , , , , , and . SiPS, page 675-680. IEEE, (2007)A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile., , , and . APCCAS, page 760-763. IEEE, (2006)Fast intra prediction for HEVC based on pixel gradient statistics and mode refinement., , , , and . ChinaSIP, page 514-517. IEEE, (2013)Linear adaptive search range model for uni-prediction and motion analysis for bi-prediction in HEVC., , , and . ICIP, page 3671-3675. IEEE, (2014)Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt., , and . ICIP, page 2701-2704. IEEE, (2009)Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving., , , and . IEICE Trans. Inf. Syst., 88-D (7): 1526-1537 (2005)