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An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches., , and . SIGARCH Comput. Archit. News, 35 (4): 45-52 (2007)Destructive-read in embedded DRAM, impact on power consumption., , , and . J. Embed. Comput., 2 (2): 249-260 (2006)Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination., and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 52-66. Springer, (2006)A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors., , and . HiPC, volume 4297 of Lecture Notes in Computer Science, page 22-34. Springer, (2006)An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches., , and . MEDEA@PACT, page 45-52. ACM, (2006)An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors., and . HPCA, page 2-12. IEEE Computer Society, (2007)Cache Write-Back Schemes for Embedded Destructive-Read DRAM., , and . ARCS, volume 3894 of Lecture Notes in Computer Science, page 145-159. Springer, (2006)An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, , and . SIGARCH Comput. Archit. News, 35 (4): 45--52 (2007)