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A novel design methodology for hybrid process 3D-IC., , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)Morpack Cube: A portable 3D heterogeneous system integration platform., , , , , , , , , and 1 other author(s). SoCC, page 197-202. IEEE, (2013)A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 56 (1): 123-135 (2021)Universal CMOS Diamond-Graph Circuit for Embedded Computing., , , and . SoCC, page 206-212. IEEE, (2018)A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality., , , , , , , and . VLSI Technology and Circuits, page 42-43. IEEE, (2022)A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS., , , , , , , and . ESSCIRC, page 107-110. IEEE, (2021)The design and implementation of DCT/IDCT chip with novel architecture., , and . ISCAS, page 741-744. IEEE, (2000)A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow., , , , , , , and . ISSCC, page 332-333. IEEE, (2023)A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing., , , , , , , , , and 1 other author(s). ISSCC, page 44-45. IEEE, (2023)An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer., , , , , , , , , and 7 other author(s). ISCAS, page 1-4. IEEE, (2017)