( en | de | ru )

 

Disambiguation of "Possani, Vinicius N."

Author of the publication

copydeleteadd this publication to your clipboard
Majority-based Design Flow for AQFP Superconducting Family.

, , , , , , , , , , and . DATE, page 34-39. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

n n n

Vinícius Liebel

Vinícius Maran

Vinicius Malatesta

Vinicius Mariano Carvalho

 

Other publications of authors with the same name

Parallel Combinational Equivalence Checking., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3081-3092 (2020)Transistor Count Optimization in IG FinFET Network Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)Exact Benchmark Circuits for Logic Synthesis., , , , , , and . IEEE Des. Test, 37 (3): 51-58 (2020)Exploring Independent Gates in FinFET-Based Transistor Network Generation., , , , and . SBCCI, page 41:1-41:6. ACM, (2014)Improving the methodology to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2013)LUT-Based Optimization For ASIC Design Flow., , , , , , , , and . DAC, page 871-876. IEEE, (2021)Majority-based Design Flow for AQFP Superconducting Family., , , , , , , , , and 1 other author(s). DATE, page 34-39. IEEE, (2022)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , and . DAC, page 1-6. IEEE, (2020)Unlocking fine-grain parallelism for AIG rewriting., , , , , and . ICCAD, page 87. ACM, (2018)