Author of the publication

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.

, , and . SoCC, page 175-178. IEEE, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A robust ultra-low power asynchronous FIFO memory with self-adaptive power control., , and . SoCC, page 175-178. IEEE, (2008)FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration., , , and . MASCOTS, page 43-46. IEEE Computer Society, (2015)Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM., , , and . HPCA, page 143-154. IEEE Computer Society, (2013)A 65nm low power 2T1D embedded DRAM with leakage current reduction., , and . SoCC, page 207-210. IEEE, (2007)Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach., , , and . ACM Great Lakes Symposium on VLSI, page 439-442. ACM, (2018)An analytical model to estimate PCM failure probability due to process variations., and . SoCC, page 174-177. IEEE, (2011)DRAM Refresh Mechanisms, Penalties, and Trade-Offs., , , , and . IEEE Trans. Computers, 65 (1): 108-121 (2016)A fully-differential subthreshold SRAM cell with auto-compensation., and . APCCAS, page 1771-1774. IEEE, (2008)FlashStorageSim: Performance Modeling for SSD Architectures., , , and . NAS, page 1-2. IEEE Computer Society, (2017)Energy-Efficient Cached DIMM Architecture., , and . MASCOTS, page 501-503. IEEE Computer Society, (2012)