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A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.

, , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers., , , , and . ICECS, page 41-45. IEEE, (2006)A 6.5 GHz Arbitrary Digital Waveform Generator., , , and . ESSCIRC, page 482-485. IEEE, (2012)An Inverter-Based Hybrid ΔΣ Modulator., , and . ISSCC, page 492-493. IEEE, (2008)A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end., , and . ISSCC, page 62-63. IEEE, (2010)A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band., , , , and . ISSCC, page 238-599. IEEE, (2007)A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth., , and . IEEE J. Solid State Circuits, 39 (12): 2152-2160 (2004)A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS., , , , , , , and . ESSCIRC, page 491-494. IEEE, (2021)A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW., , , , , , , , , and . ESSCIRC, page 321-324. IEEE, (2022)A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction., , , , , , and . IEEE J. Solid State Circuits, 57 (12): 3768-3780 (2022)A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW., , , and . IEEE J. Solid State Circuits, 46 (12): 2857-2868 (2011)