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Disambiguation of "Wu, Shianling"

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Collaboration between Industry and Academia in Test Research.

, , , , , and . Asian Test Symposium, page 17. IEEE Computer Society, (2000)

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Jinglan Wu

Recovery of citric acid from fermentation broth using simulated moving bed technology: = Reinigung von Zitronensäure aus Fermentationslösung durch kontinuierliche Chromatographie. Uni Erlangen-Nürnberg, (2009)

Zongmin Wu

Dagang Wu

Weijia Wu

Hongzhong Wu

 

Other publications of authors with the same name

At-Speed Logic BIST Architecture for Multi-Clock Designs., , , , and . ICCD, page 475-478. IEEE Computer Society, (2005)A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing., , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)A Sequential Circuit Test Generation System., and . ITC, page 57-61. IEEE Computer Society, (1985)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Des. Test Comput., 25 (2): 122-130 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)Lessons Learned from Practical Applications of BIST/B-S Technology., , , and . Asian Test Symposium, page 251-257. IEEE Computer Society, (1996)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)