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Disambiguation of "Wang, Laung-Terng"

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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

, , , , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (3): 455-463 (2011)

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Andy Ch Laungani

Harn-Jing Terng

Terng-Yaw Lin

Wang Wang

Linfang Wang

Investigation of the functions of 53BP1 in DNA demethylation. Uni Marburg, (2009)
 

Other publications of authors with the same name

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , and . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)Self-Testing of Embedded RAMs., and . ITC, page 148-156. IEEE Computer Society, (1984)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)Low-capture-power test generation for scan-based at-speed testing., , , , , , and . ITC, page 10. IEEE Computer Society, (2005)CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing., , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 942-953 (2017)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Des. Test Comput., 25 (2): 122-130 (2008)