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Disambiguation of "Chen, Gregory K."

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A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme.

, , , , , and . ISCAS, page 69-72. IEEE, (2011)

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Chen Chen

Chen Chen

Robert Gregory

Isa Gregory

Gregory Kroon

 

Other publications of authors with the same name

CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (1): 42-49 (2011)Centip3De: A 64-Core, 3D Stacked Near-Threshold System., , , , , , , , , and 5 other author(s). IEEE Micro, 33 (2): 8-16 (2013)A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme., , , , , and . ISCAS, page 69-72. IEEE, (2011)Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells., , , , , , , , , and . ISSCC, page 288-289. IEEE, (2010)Centip3De: a many-core prototype exploring 3D integration and near-threshold computing., , , , , , , , , and 5 other author(s). Commun. ACM, 56 (11): 97-104 (2013)A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS., , , , and . CICC, page 1-4. IEEE, (2010)microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware., , , , , and . ESSCIRC, page 421-424. IEEE, (2023)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI., , , , , , , , , and 6 other author(s). FPGA, page 119. ACM, (2019)