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Disambiguation of "Kelefouras, Vasilios I."

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Workflow Simulation Aware and Multi-threading Effective Task Scheduling for Heterogeneous Computing.

, and . HiPC, page 215-224. IEEE, (2018)

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Vasilios Trakas

Vasilios Katos

Vasilios Gemenetzis

Vasilios Zorkadis

Vasilios Darlagiannis

 

Other publications of authors with the same name

Array Size Computation under Uniform Overlapping and Irregular Accesses., , , and . ACM Trans. Design Autom. Electr. Syst., 21 (2): 22:1-22:35 (2016)On the exploitation of a high-throughput SHA-256 FPGA design for HMAC., , , , and . ACM Trans. Reconfigurable Technol. Syst., 5 (1): 2:1-2:28 (2012)A methodology correlating code optimizations with data memory accesses, execution time and energy consumption., and . J. Supercomput., 75 (10): 6710-6745 (2019)Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints., , , , and . ACM Trans. Archit. Code Optim., 10 (2): 6:1-6:25 (2013)A methodology for speeding up loop kernels by exploiting the software information and the memory architecture., , and . Comput. Lang. Syst. Struct., (2015)A Practical Approach for Employing Tensor Train Decomposition in Edge Devices., , , and . Int. J. Parallel Program., 52 (1): 20-39 (April 2024)Workflow simulation and multi-threading aware task scheduling for heterogeneous computing., and . J. Parallel Distributed Comput., (2022)Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes., , , and . ACM Trans. Design Autom. Electr. Syst., 19 (1): 4:1-4:30 (2013)XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems., , , , , , , , , and 16 other author(s). DATE, page 1-5. IEEE, (2022)Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management., , and . ISVLSI, page 477-482. IEEE Computer Society, (2017)