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Disambiguation of "Yamaguchi, Takahiro J."

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A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters.

, , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (3): 777-780 (2014)

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Shigeo Yamaguchi

Takahiro Kato

Takahiro Moriyama

Fabian Yamaguchi

Ichiro Yamaguchi

 

Other publications of authors with the same name

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer., , , and . ISCAS, page 93-96. IEEE, (2014)Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology., , , , and . ICECS, page 220-223. IEEE, (2011)Multi-bit Sigma-Delta TDC Architecture with Improved Linearity., , , , , , , , , and 3 other author(s). J. Electron. Test., 29 (6): 879-892 (2013)A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters., , , , , and . IEEE Trans. Circuits Syst., 67-I (12): 5561-5573 (2020)Application of a continuous-time level crossing quantization method for timing noise measurements., , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2011)A novel test structure for measuring the threshold voltage variance in MOSFETs., , , and . ITC, page 1-8. IEEE Computer Society, (2013)A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter., , , , and . ITC, page 717-725. IEEE Computer Society, (2002)Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements., , , , and . ITC, page 58-66. IEEE Computer Society, (2003)A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems., , , , , , and . ITC, page 77-84. IEEE Computer Society, (2004)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)