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Disambiguation of "Huylenbroeck, Stefaan Van"

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Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module.

, , , , , , , , , , , , and . 3DIC, page 1-4. IEEE, (2016)

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Stefaan Van der Vekens

Stefaan Bergé

Stefaan Haspeslagh

Stefaan Lecleir

Stefaan De Neve

 

Other publications of authors with the same name

Active-lite interposer for 2.5 & 3D integration., , , , , , , , , and 5 other author(s). VLSIC, page 222-. IEEE, (2015)Process Complexity and Cost Considerations of Multi-Layer Die Stacks., , , , , , , , , and 5 other author(s). 3DIC, page 1-6. IEEE, (2019)Reliability challenges for barrier/liner system in high aspect ratio through silicon vias., , , , , , , , , and . Microelectron. Reliab., 54 (9-10): 1949-1952 (2014)Impact of oxide liner properties on TSV Cu pumping and TSV stress., , , , , , , , , and 2 other author(s). IRPS, page 4. IEEE, (2015)Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques., , , and . ESSDERC, page 221-225. IEEE, (2012)TSV process-induced MOS reliability degradation., , , , , , and . IRPS, page 5. IEEE, (2018)Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module., , , , , , , , , and 3 other author(s). 3DIC, page 1-4. IEEE, (2016)Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias., , , , , , and . 3DIC, page 1-4. IEEE, (2014)Pushing the speed limits of SiGe: C HBTs up to 0.5 Terahertz., , , , , , , , and . CICC, page 347-354. IEEE, (2009)