Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Minimal Test for Coupling Faults in Word-Oriented Memories., , and . DATE, page 944-948. IEEE Computer Society, (2002)Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs., and . DATE, page 496-503. IEEE Computer Society, (2001)Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation., , and . Asian Test Symposium, page 185-191. IEEE Computer Society, (1999)A Fault Primitive Based Analysis of Linked Faults in RAMs., , and . MTDT, page 33-. IEEE Computer Society, (2003)Influence of Bit Line Twisting on the Faulty Behavior of DRAMs., , , and . MTDT, page 32-37. IEEE Computer Society, (2004)Industrial evaluation of stress combinations for march tests applied to SRAMs., and . ITC, page 983-992. IEEE Computer Society, (1999)Coping with Re-usability Using Sequential ATPG: A Practical Case Study., , , , and . ITC, page 252-261. IEEE Computer Society, (1995)Semiconductor manufacturing process monitoring using built-in self-test for embedded memories., , , , and . ITC, page 872-881. IEEE Computer Society, (1998)Consequences of port restrictions on testing two-port memories., and . ITC, page 63-72. IEEE Computer Society, (1998)Test Pattern Generation with Restrictors., , and . ITC, page 598-605. IEEE Computer Society, (1993)