( en | de | ru )

 

Disambiguation of "Jayakumar, Nikhil"

Author of the publication

copydeleteadd this publication to your clipboard
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.

, , and . ISLPED, page 111-114. ACM, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nikhil Sasidharan

Tammana Jayakumar

Nikhil Ratanje

Nikhil Jethava

Nikhil Karamchandani

 

Other publications of authors with the same name

High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems., , , , and . VLSI Signal Processing, 49 (1): 185-206 (2007)A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations., , , and . Integr., 41 (3): 399-412 (2008)A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 269-277 (2009)A design flow to optimize circuit delay by using standard cells and PLAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2006)A Structured ASIC Design Approach Using Pass Transistor Logic., , and . ISCAS, page 1787-1790. IEEE, (2007)A Predictably Low-Leakage ASIC Design Style., and . IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 276-285 (2007)Circuit-Level Design Approaches for Radiation-Hard Digital Electronics., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (6): 781-792 (2009)A variation tolerant subthreshold design approach., and . DAC, page 716-719. ACM, (2005)A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents., , and . DAC, page 43-46. ACM, (2005)A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty., and . ACM Trans. Design Autom. Electr. Syst., 16 (1): 9 (2010)