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Design and performance of networks for super-, cluster-, and grid-computing: Part II.

, , and . J. Parallel Distributed Comput., 65 (11): 1301-1304 (2005)

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Improving the performance of deadlock recovery based routing in irregular mesh NoCs using added mesh-like links., , and . ISCAS, page 3236-3239. IEEE, (2010)Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube., and . Asia-Pacific Computer Systems Architecture Conference, volume 3189 of Lecture Notes in Computer Science, page 349-362. Springer, (2004)High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement., , and . ISLPED, page 79-84. IEEE/ACM, (2011)An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators., , , and . ISLPED, page 249-254. IEEE, (2015)Design for scalability in enterprise SSDs., , and . PACT, page 417-430. ACM, (2014)Traffic-aware buffer reconfiguration in on-chip networks., and . VLSI-SoC, page 201-206. IEEE, (2015)Chapter Six - Topology Specialization for Networks-on-Chip in the Dark Silicon Era., and . Advances in Computers, (2018)Chapter One - Dark Silicon and the History of Computing., and . Advances in Computers, (2018)Analytical modelling of wormhole-routed k-ary n-cubes in the presence of matrix-transpose traffic., , and . J. Parallel Distributed Comput., 63 (4): 396-409 (2003)Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology., , and . Microprocess. Microsystems, (2016)