( en | de | ru )

 

Disambiguation of "Takizawa, Hiroyuki"

Author of the publication

copydeleteadd this publication to your clipboard
Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture.

, , , , , , and . ISPA, page 335-342. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hiroyuki Tan

Hiroyuki Kobayashi

Chieko Takizawa

Hiroyuki Isobe

Hiroyuki Okamuro

 

Other publications of authors with the same name

Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems., , , and . Supercomput. Front. Innov., 7 (1): 71-90 (2020)Hierarchical parallel processing of large scale data clustering on a PC cluster with GPU co-processing., and . J. Supercomput., 36 (3): 219-234 (2006)A Machine Learning-Based Approach for Selecting SpMV Kernels and Matrix Storage Formats., , , and . IEICE Trans. Inf. Syst., 101-D (9): 2307-2314 (2018)Peachy Parallel Assignments (EduHPC 2019)., , , , , , , , , and 2 other author(s). EduHPC@SC, page 75-83. IEEE, (2019)Design and evaluation of a media-oriented vector processor with a multi-banked cache memory., , , , and . ESTIMedia, page 78-87. IEEE, (2013)Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs., , and . FPT, page 378-380. IEEE, (2018)A cache partitioning mechanism to protect shared data for CMPs., , , , and . COOL Chips, page 1-2. IEEE Computer Society, (2016)A media-oriented vector architectural extension with a high bandwidth cache system., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)3D on-chip memory for the vector architecture., , , and . 3DIC, page 1-6. IEEE, (2009)A Directive Generation Approach Using User-Defined Rules., , , and . CANDAR, page 515-521. IEEE Computer Society, (2016)