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Statistical logic cell delay analysis using a current-based model., , and . DAC, page 253-256. ACM, (2006)A Method of Via Variation Induced Delay Computation., , , , , , , and . DATE, page 1712-1713. IEEE, (2020)Parameterized Non-Gaussian Variational Gate Timing Analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (8): 1495-1508 (2007)Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 92-103 (2011)A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers., , and . ICCAD, page 504-509. IEEE Computer Society / ACM, (2003)Crosstalk timing windows overlap in statistical static timing analysis., and . ISQED, page 245-251. IEEE, (2013)A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect., , , and . DATE, page 568-573. ACM, (2008)VGTA: Variation Aware Gate Timing Analysis., , and . ICCD, page 351-356. IEEE Computer Society, (2005)Non-gaussian statistical interconnect timing analysis., , and . DATE, page 533-538. European Design and Automation Association, Leuven, Belgium, (2006)Lifetime-aware intrusion detection under safeguarding constraints., , and . IPSN, page 189-194. IEEE, (2005)