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Statistical logic cell delay analysis using a current-based model., , и . DAC, стр. 253-256. ACM, (2006)Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling., , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 92-103 (2011)A Method of Via Variation Induced Delay Computation., , , , , , , и . DATE, стр. 1712-1713. IEEE, (2020)Parameterized Non-Gaussian Variational Gate Timing Analysis., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (8): 1495-1508 (2007)A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers., , и . ICCAD, стр. 504-509. IEEE Computer Society / ACM, (2003)Crosstalk timing windows overlap in statistical static timing analysis., и . ISQED, стр. 245-251. IEEE, (2013)Non-gaussian statistical interconnect timing analysis., , и . DATE, стр. 533-538. European Design and Automation Association, Leuven, Belgium, (2006)A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect., , , и . DATE, стр. 568-573. ACM, (2008)VGTA: Variation Aware Gate Timing Analysis., , и . ICCD, стр. 351-356. IEEE Computer Society, (2005)Power optimal MTCMOS repeater insertion for global buses., , и . ISLPED, стр. 98-103. ACM, (2007)