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Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.

, , , and . ICSAMOS, page 118-124. IEEE, (2009)

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Voltage island management in near threshold manycore architectures to mitigate dark silicon., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Guest Editorial: Special Issue on Computing Frontiers., , , and . Int. J. Parallel Program., 46 (2): 333-335 (2018)Multi-objective design space exploration of embedded systems., , and . J. Embed. Comput., 1 (3): 305-316 (2005)Floorplan-aware hierarchical NoC topology with GALS interfaces., , , , , , and . ISCAS, page 652-655. IEEE, (2012)An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods., , and . ICSAMOS, page 150-157. IEEE, (2008)Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip., , , , , , and . NoCArc@MICRO, page 31-36. ACM, (2011)mARGOt: A Dynamic Autotuning Framework for Self-Aware Approximate Computing., , , and . IEEE Trans. Computers, 68 (5): 713-728 (2019)Design Space Pruning and Computational Workload Splitting for Autotuning OpenCL Applications., , , and . RAPIDO, page 4:1-4:6. ACM, (2018)A security monitoring service for NoCs., , and . CODES+ISSS, page 197-202. ACM, (2008)DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (2): 293-306 (2015)