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Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.

, , , and . ICSAMOS, page 118-124. IEEE, (2009)

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Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors., , , , and . ARCS Workshops, page 325-331. VDE Verlag, (2010)Branch prediction techniques for low-power VLIW processors., , , , and . ACM Great Lakes Symposium on VLSI, page 225-228. ACM, (2003)ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models., , , and . Parallel Comput., 39 (9): 504-519 (2013)A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems., , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 249-258. Springer, (2003)Reducing the complexity of instruction-level power models for VLIW processors., , , , , and . Des. Autom. Embed. Syst., 10 (1): 49-67 (2005)On the spectral features of robust probing security., and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020 (4): 24-48 (2020)An F-algebra for analysing information leaks in the presence of glitches.. IACR Cryptol. ePrint Arch., (2020)OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 740-753 (2012)Linking run-time resource management of embedded multi-core platforms with automated design-time exploration., , , , , and . IET Comput. Digit. Tech., 5 (2): 123-135 (2011)A correlation-based design space exploration methodology for multi-processor systems-on-chip., , , , , and . DAC, page 120-125. ACM, (2010)