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Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1872-1885 (2019)

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GhostBusters: Mitigating Spectre Attacks on a DBT-Based Processor.. DATE, page 927-932. IEEE, (2020)Accélération matérielle pour la traduction dynamique de programmes binaires. (Hardware Accelerated Dynamic Binary Translation).. University of Rennes 1, France, (2018)Toward Speculative Loop Pipelining for High-Level Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 4229-4239 (2020)Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis., , and . FPT, page 1-6. IEEE, (2022)SpecHLS: Speculative Accelerator Design Using High-Level Synthesis., , and . IEEE Micro, 42 (5): 99-107 (2022)Attack Detection Through Monitoring of Timing Deviations in Embedded Real-Time Systems., , and . ECRTS, volume 165 of LIPIcs, page 8:1-8:22. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2020)Hardware-accelerated dynamic binary translation., , and . DATE, page 1062-1067. IEEE, (2017)RT-DFI: Optimizing Data-Flow Integrity for Real-Time Systems., , , , and . ECRTS, volume 231 of LIPIcs, page 18:1-18:24. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2022)A Unified Memory Dependency Framework for Speculative High-Level Synthesis., , and . CC, page 13-25. ACM, (2024)What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications., , , and . ICCAD, page 1-8. ACM, (2019)