Author of the publication

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1872-1885 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Reconfigurable Parallel Disk System for Filtering Genomic Banks., , , and . Engineering of Reconfigurable Systems and Algorithms, page 154-166. CSREA Press, (2003)SpecHLS: Speculative Accelerator Design Using High-Level Synthesis., , and . IEEE Micro, 42 (5): 99-107 (2022)Special Issue on Applied Reconfigurable Computing., and . J. Signal Process. Syst., 94 (9): 847-848 (2022)Efficient hardware implementation of data-flow parallel embedded systems., , and . ICSAMOS, page 364-371. IEEE, (2012)Superword level parallelism aware word length optimization., and . DATE, page 1068-1073. IEEE, (2017)FCCMS and the Memory Wall., and . FCCM, page 329-330. IEEE Computer Society, (2000)GeCoS: A framework for prototyping custom hardware design flows., , , , , , , , , and 3 other author(s). SCAM, page 100-105. IEEE Computer Society, (2013)Ultra Low-power FSM for Control Oriented Applications., , and . ISCAS, page 1577-1580. IEEE, (2009)Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1872-1885 (2019)Enabling Overclocking Through Algorithm-Level Error Detection., , and . FPT, page 174-181. IEEE, (2018)