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FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision., , , , , и . A-SSCC, стр. 47-50. IEEE, (2018)Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN., , , , , , и . AICAS, стр. 1-4. IEEE, (2021)Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization., , , и . ISCAS, стр. 1-5. IEEE, (2021)A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique., , , , , и . ASP-DAC, стр. 5-6. IEEE, (2016)A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular., , , , , , , и . ESSCIRC, стр. 76-79. IEEE, (2015)An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer., , , , , , , , , и 18 other автор(ы). IEEE J. Solid State Circuits, 53 (12): 3688-3699 (2018)Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision., , , , , и . ISCAS, стр. 1. IEEE, (2019)A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB., , , , , , , , и . IEEE J. Solid State Circuits, 51 (7): 1630-1640 (2016)A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS., , , , , , , и . IEICE Trans. Electron., 101-C (4): 187-196 (2018)A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI., , , , , , , , и . IEICE Trans. Electron., 99-C (6): 632-640 (2016)