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A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (5): 1164-1174 (2020)

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High performance multirate SC circuits with predictive correlated double sampling technique., , and . ISCAS (2), page 77-80. IEEE, (1999)A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator., , and . ISCAS, IEEE, (2006)A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications., , and . ISCAS (4), page 417-420. IEEE, (2004)A 0.4V 4.8μW 16MHz CMOS crystal oscillator achieving 74-fold startup-time reduction using momentary detuning., , and . ISCAS, page 1-4. IEEE, (2017)A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages., , , , , , and . A-SSCC, page 145-148. IEEE, (2016)A highly-linear ultra-wideband balun-LNA for cognitive radios., , , and . EUROCON, page 1-4. IEEE, (2011)A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS., , and . ISSCC, page 448-449. IEEE, (2013)2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF., , and . ISSCC, page 1-3. IEEE, (2015)Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques., , , , , , and . ASP-DAC, page 15-16. IEEE, (2016)Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring., , , and . ASP-DAC, page 21-22. IEEE, (2016)