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A Method for the Systematic Generation of Audit Logs in a Digital Preservation Environment and Its Experimental Implementation In a Production Ready System.

H. Xu, J. Coposky, D. Bedard, J. Ward, T. Russell, A. Rajasekar, R. Moore, B. Keller, and Z. Greer. iPRES, (2015)

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Ben Novak

Ben Schöttker

Ben Schacher

Ben Schloesser

Ben Schmehe

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Reply to discussion by B. Keller and R. Nance.B. Keller, and R. Nance. Journal of Software Maintenance, 7 (5): 379-380 (1995)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI.M. Blagojevic, M. Cochet, B. Keller, P. Flatresse, A. Vladimirescu, and B. Nikolic. VLSI Circuits, page 1-2. IEEE, (2016)HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression.J. Gu, B. Keller, J. Kossaifi, A. Anandkumar, B. Khailany, and D. Pan. CoRR, (2022)A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojevic, S. Bailey, P. Chiu, D. Dabbelt and 4 other author(s). IEEE J. Solid State Circuits, 52 (7): 1863-1875 (2017)Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.S. Dai, A. Klinefelter, H. Ren, R. Venkatesan, B. Keller, N. Pinckney, and B. Khailany. CoRR, (2021)MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.V. Chhabria, Y. Zhang, H. Ren, B. Keller, B. Khailany, and S. Sapatnekar. DATE, page 1825-1828. IEEE, (2021)Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).Y. Zhang, H. Ren, B. Keller, and B. Khailany. ICCAD, page 70:1-70:4. IEEE, (2020)Clumpy high-z galaxies as a testbed for feedback-regulated galaxy formationL. Mayer, V. Tamburello, A. Lupi, B. Keller, J. Wadsley, and P. Madau. (2016)cite arxiv:1606.06739Comment: submitted to ApJ Letters, comments welcome.A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm.B. Keller, R. Venkatesan, S. Dai, S. Tell, B. Zimmer, C. Sakr, W. Dally, C. Gray, and B. Khailany. IEEE J. Solid State Circuits, 58 (4): 1129-1141 (2023)A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.J. Wright, C. Schmidt, B. Keller, D. Dabbelt, J. Kwak, V. Iyer, N. Mehta, P. Chiu, S. Bailey, K. Asanovic and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)

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Disambiguation of "Keller, Ben"

Please choose a person to relate this publication to

Ben Novak

Ben Schöttker

Ben Schacher

Ben Schloesser

Ben Schmehe

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Keller, Ben"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Method for the Systematic Generation of Audit Logs in a Digital Preservation Environment and Its Experimental Implementation In a Production Ready System.

Please choose a person to relate this publication to

Ben Novak

Ben Schöttker

Ben Schacher

Ben Schloesser

Ben Schmehe

Other publications of authors with the same name

Disambiguation