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14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC., , , , , , , , , and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 58 (4): 1074-1086 (2023)A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI., , , , , and . ESSCIRC, page 153-162. IEEE, (2017)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components., , , , , , , , , and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Resilient Low Voltage Accelerators for High Energy Efficiency., , , , , , , , and . HPCA, page 147-158. IEEE, (2019)