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A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI.

, , , , , , and . ISSCC, page 370-371. IEEE, (2010)

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A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI., , , , , , and . ISSCC, page 370-371. IEEE, (2010)A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS., , , , , and . CICC, page 1-4. IEEE, (2012)A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 49 (1): 127-139 (2014)A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (4): 814-827 (2015)A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems., , , , , , , , , and 6 other author(s). ISSCC, page 306-307. IEEE, (2013)A 40-Gb/s serial link transceiver in 28-nm CMOS technology., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)