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Disambiguation of "Sobue, Kazuki"

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Parallel gain enhancement technique for switched-capacitor circuits.

, , , , , , and . CICC, page 1-4. IEEE, (2013)

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Other publications of authors with the same name

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier., , , , and . VLSIC, page 1-2. IEEE, (2014)Ring Amplifiers for Switched Capacitor Circuits., , , , , and . IEEE J. Solid State Circuits, 47 (12): 2928-2942 (2012)An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 61-73 (2018)A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR., , , and . VLSI Circuits, page 205-206. IEEE, (2018)A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays., , , , , , , and . ESSCIRC, page 221-224. IEEE, (2015)A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers., , , , , and . VLSIC, page 32-33. IEEE, (2012)A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL., , , , and . CICC, page 1-4. IEEE, (2017)A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW., , , , , and . CICC, page 1-4. IEEE, (2017)A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator., , , , and . IEEE J. Solid State Circuits, 55 (2): 426-438 (2020)A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW., , , , , , , , , and 1 other author(s). A-SSCC, page 1-3. IEEE, (2021)