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Disambiguation of "Mahmoodi-Meimand, Hamid"

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Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (12): 1859-1880 (2005)

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Benjamin Mahmoodi

Mehrdad Mahmoodi

Zahra Hamidi

Ahmad Hamidov

Saeed Hamid-Khani

 

Other publications of authors with the same name

Efficient power clock generation for adiabatic logic., and . ISCAS (4), page 642-645. IEEE, (2001)Leakage Current in Deep-Submicron CMOS Circuits., , and . J. Circuits Syst. Comput., 11 (6): 575-600 (2002)A process-tolerant cache architecture for improved yield in nanoscale technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (1): 27-38 (2005)Dual-edge triggered level converting flip-flops., and . ISCAS (2), page 661-664. IEEE, (2004)A novel synthesis approach for active leakage power reduction using dynamic supply gating., , , , and . DAC, page 479-484. ACM, (2005)A Novel Low-Power Scan Design Technique Using Supply Gating., , , , and . ICCD, page 60-65. IEEE Computer Society, (2004)Energy recovery clocked dynamic logic., , , and . ACM Great Lakes Symposium on VLSI, page 468-471. ACM, (2005)Low power synthesis of dynamic logic circuits using fine-grained clock gating., , , and . DATE, page 862-867. European Design and Automation Association, Leuven, Belgium, (2006)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1286-1295 (2005)Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits., , and . CICC, page 17-20. IEEE, (2004)