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Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product.

, , , , , and . J. Signal Process. Syst., 95 (7): 815-829 (July 2023)

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FPGA-based design of a self-checking TMR voter., and . FPL, page 1-4. IEEE, (2017)Design of a Mutated Adder and Its Optimization Using ILP Formulation., , , and . IEICE Trans. Inf. Syst., 88-D (7): 1506-1508 (2005)Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization., , and . Microelectron. Reliab., (2016)Adaptive least significant bit matching revisited with the help of error images., and . Secur. Commun. Networks, 8 (3): 510-515 (2015)A Floating Point Vectoring Algorithm Based on Fast Rotations., , and . EUROMICRO, page 1140-. IEEE Computer Society, (1999)A Design Method for Heterogeneous Adders., , , and . ICESS, volume 4523 of Lecture Notes in Computer Science, page 121-132. Springer, (2007)SVD by constant-factor-redundant-CORDIC., and . IEEE Symposium on Computer Arithmetic, page 264-271. IEEE, (1991)An Autonomous Self-Aware and Adaptive Fault Tolerant Routing Technique for Wireless Sensor Networks., and . Sensors, 15 (8): 20316-20354 (2015)A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithm., , , and . J. Supercomput., 79 (11): 12042-12073 (2023)An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilities., and . FPT, page 301-304. IEEE, (2012)