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DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.

M. Abdelfattah, D. Han, A. Bitar, R. DiCecco, S. O'Connell, N. Shanker, J. Chu, I. Prins, J. Fender, A. Ling, and G. Chiu. FPL, page 411-418. IEEE Computer Society, (2018)

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Andrew C Brunson

Andrew C Oates

Andrew C Rouse

Dchi-ling Ling

Paul Ling

Other publications of authors with the same name

Harnessing Numerical Flexibility for Deep Learning on FPGAs.A. Ling, M. Abdelfattah, S. O'Connell, A. Bitar, D. Han, R. DiCecco, S. Subhaschandra, C. Johnson, D. Denisenko, J. Fender and 1 other author(s). HEART, page 1:1-1:3. ACM, (2018)An OpenCL(TM) Deep Learning Accelerator on Arria 10.U. Aydonat, S. O'Connell, D. Capalija, A. Ling, and G. Chiu. CoRR, (2017)Scalable Synthesis and Clustering Techniques Using Decision Diagrams.A. Ling, J. Zhu, and S. Brown. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (3): 423-435 (2008)Harnessing the Power of FPGAs with the Intel FPGA SDK for OpenCL™.B. Sinclair, A. Ling, and G. Paikin. IWOCL, page 19:1. ACM, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.M. Abdelfattah, D. Han, A. Bitar, R. DiCecco, S. O'Connell, N. Shanker, J. Chu, I. Prins, J. Fender, A. Ling and 1 other author(s). FPL, page 411-418. IEEE Computer Society, (2018)BddCut: Towards Scalable Symbolic Cut Enumeration.A. Ling, J. Zhu, and S. Brown. ASP-DAC, page 408-413. IEEE Computer Society, (2007)Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming Processors.D. Abts, I. Ahmed, A. Bitar, M. Boyd, J. Kim, G. Kimmell, and A. Ling. DSN (Supplements), page 19-22. IEEE, (2022)FPGA PLB Evaluation using Quantified Boolean Satisfiability.A. Ling, D. Singh, and S. Brown. FPL, page 19-24. IEEE, (2005)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, S. Shumarayev and 1 other author(s). FPGA, page 287. ACM, (2018)

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Disambiguation of "Ling, Andrew C."

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DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.

Please choose a person to relate this publication to

Andrew C Brunson

Andrew C Oates

Andrew C Rouse

Dchi-ling Ling

Paul Ling

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ling, Andrew C."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.

Please choose a person to relate this publication to

Andrew C Brunson

Andrew C Oates

Andrew C Rouse

Dchi-ling Ling

Paul Ling

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration.