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Disambiguation of "Dutt, Nikil D."

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DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era.

, , , , and . ACM Trans. Archit. Code Optim., 12 (3): 27:1-27:26 (2015)

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Martha Duttle

Johann Duttlinger

Ludwig Duttka

Renate Düttmann

Martin Dütting

 

Other publications of authors with the same name

Customizing Software Toolkits for Embedded Systems-On-Chip., , and . DIPES, volume 189 of IFIP Conference Proceedings, page 87-98. Kluwer, (2000)A hypergraph-based model for port allocation on multiple-register-file VLIW architectures., , and . Int. J. Parallel Program., 23 (6): 499-513 (1995)Retargetable pipeline hazard detection for partially bypassed processors., , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (8): 791-801 (2006)The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing., , , , , , , , , and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 10 (1): 250-266 (2022)Robust Face Recognition Against Soft-errors Using a Cross-layer Approach., , , , and . Int. J. Comput. Commun. Control, 11 (5): 657-665 (2016)Endurance-Aware Mapping of Spiking Neural Networks to Neuromorphic Hardware., , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (2): 288-301 (2022)Efficient Personalized Learning for Wearable Health Applications using HyperDimensional Computing., , , , , , and . CoRR, (2022)Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 944-951 (2018)Fast Configurable-Cache Tuning With a Unified Second-Level Cache., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 80-91 (2009)Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution., , , and . Des. Autom. Embed. Syst., 17 (2): 377-409 (2013)