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DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era.

, , , , and . ACM Trans. Archit. Code Optim., 12 (3): 27:1-27:26 (2015)

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Reliable On-Chip Memory Design for CMPs.. SRDS, page 487-488. IEEE Computer Society, (2012)Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation., , and . ACM Trans. Embed. Comput. Syst., 14 (2): 32:1-32:24 (2015)DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era., , , , and . ACM Trans. Archit. Code Optim., 12 (3): 27:1-27:26 (2015)Resilient On-Chip Memory Design in the Nano Era.. University of California, Irvine, USA, (2015)Multi-Layer Memory Resiliency., , , , , and . DAC, page 48:1-48:6. ACM, (2014)A novel NoC-based design for fault-tolerance of last-level caches in CMPs., , and . CODES+ISSS, page 63-72. ACM, (2012)Exploiting Partially-Forgetful Memories for Approximate Computing., , and . IEEE Embed. Syst. Lett., 7 (1): 19-22 (2015)Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches., , , , and . DAC, page 100:1-100:6. ACM, (2014)FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation., , and . CASES, page 95-104. ACM, (2011)Modeling and analysis of fault-tolerant distributed memories for networks-on-chip., , and . DATE, page 1605-1608. EDA Consortium San Jose, CA, USA / ACM DL, (2013)