( en | de | ru )

 

Disambiguation of "Govindarajan, Ramaswamy"

Author of the publication

copydeleteadd this publication to your clipboard
Improving power efficiency with compiler-assisted cache replacement.

, , , and . J. Embed. Comput., 1 (4): 487-499 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nambirajan Govindarajan

Parameswari Govindarajan

Ramaswamy Lakshmanan

Thirupugal Govindarajan

Annette Ramaswamy

 

Other publications of authors with the same name

A Comprehensive Analytical Performance Model of DRAM Caches., , and . ICPE, page 157-168. ACM, (2015)A Large Context Multithreaded Architecture., and . CONPAR, volume 634 of Lecture Notes in Computer Science, page 423-428. Springer, (1992)Instruction Scheduling.. The Compiler Design Handbook, CRC Press, (2002)An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining., , and . LCPC, volume 1033 of Lecture Notes in Computer Science, page 16-30. Springer, (1995)Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory., , , and . Int. J. Parallel Program., 28 (1): 1-46 (2000)HAShCache: Heterogeneity-Aware Shared DRAMCache for Integrated Heterogeneous Systems., and . ACM Trans. Archit. Code Optim., 14 (4): 51:1-51:26 (2017)Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops., , , and . CGO, page 175-188. IEEE Computer Society, (2004)ANATOMY: an analytical model of memory system performance., , , and . SIGMETRICS, page 505-517. ACM, (2014)A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors., , , and . IEEE PACT, page 78-89. IEEE Computer Society, (1997)An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams., , , and . IPPS/SPDP, page 168-175. IEEE Computer Society, (1998)