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3D die-stacked DRAM thermal management via task allocation and core pipeline control.

, , , and . IEICE Electron. Express, 15 (3): 20171253 (2018)

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A Haar Classifier Accelerator with Reduced Multiplexer Usage., and . ISOCC, page 399-400. IEEE, (2021)Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems., , , and . ISOCC, page 401-402. IEEE, (2021)A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000., , , , , and . FGIT-FGCN (2), volume 120 of Communications in Computer and Information Science, page 343-346. Springer, (2010)An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing., , , , , and . FGIT-FGCN (1), volume 265 of Communications in Computer and Information Science, page 136-146. Springer, (2011)Hardware-friendly architecture for a pseudo 2D weighted median filter based on sparse-window approach., , , and . Multim. Tools Appl., 80 (26): 34221-34236 (2021)An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems., and . Multim. Tools Appl., 76 (17): 17907-17922 (2017)Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors., , and . J. Supercomput., 74 (12): 6665-6690 (2018)Hardware Architecture of a Haar Classifier Based Face Detection System Using a Skip Scheme., , , and . ISCAS, page 1-4. IEEE, (2021)A study of partitioned DIMM tree management for multimedia server systems., , and . Multim. Tools Appl., 76 (17): 17937-17954 (2017)An Improved Stereo Matching Algorithm with Robustness to Noise Based on Adaptive Support Weight., and . J. Inf. Process. Syst., 13 (2): 256-267 (2017)