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Disambiguation of "Mandal, Swagata"

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FPGA Based Novel High Speed DAQ System Design with Error Correction.

, , , , , and . ISVLSI, page 80-85. IEEE Computer Society, (2015)

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Avradip Mandal

Soumyajit Mandal

Dipankar Mandal

Ranadip Mandal

Oliver Mandal

 

Other publications of authors with the same name

iMACE: In-Memory Acceleration of Classic McEliece Encoder., , , , and . ISVLSI, page 513-518. IEEE, (2019)Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture., , and . CoRR, (2022)Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA., , , , and . VLSID, page 257-262. IEEE, (2019)Lightweight ASIC Implementation of AEGIS-128., , , and . ISVLSI, page 251-256. IEEE Computer Society, (2018)Joint power and channel allocation for outage probability minimization in cognitive radio ad hoc networks., , and . COMSNETS, page 1-7. IEEE, (2013)FPGA Based Novel High Speed DAQ System Design with Error Correction., , , , , and . ISVLSI, page 80-85. IEEE Computer Society, (2015)FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code., , , , and . ATS, page 169-174. IEEE Computer Society, (2015)Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA., , , , and . CoRR, (2018)ReRAM-based In-Memory Computation of Galois Field arithmetic., , , and . VLSI-SoC, page 1-6. IEEE, (2018)ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code., , , and . VLSI-SoC (Selected Papers), volume 561 of IFIP Advances in Information and Communication Technology, page 128-146. Springer, (2018)