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Disambiguation of "Chaourani, Panagiotis"

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Regional Clock Tree Generation by Abutment in Synchoros VLSI Design.

, , , and . CoRR, (2019)

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Panagiotis Mitsakis

Panagiotis Zacharopoulos

Panagiotis Theodorou

Panagiotis Tokmakidis

Panagiotis Vougioukas

 

Other publications of authors with the same name

An Evaluation of the Equivalent Inverter Modeling Approach., , , , , , , and . Circuits Syst. Signal Process., 37 (7): 2665-2693 (2018)Clock Tree Generation by Abutment in Synchoros VLSI Design., , , and . NorCAS, page 1-7. IEEE, (2021)A study for replacing CMOS gates by equivalent inverters., , , , and . ISCAS, page 1838-1841. IEEE, (2015)A unified CMOS inverter model for planar and FinFET nanoscale technologies., and . DDECS, page 242-245. IEEE Computer Society, (2014)Pass Transistor Operation Modeling for Nanoscale Technologies., , , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 53-62. Springer, (2011)An analytical model for the CMOS inverter., , , , , and . PATMOS, page 1-6. IEEE, (2014)Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 468-480 (2019)Clock tree generation by abutment in synchoros VLSI design., , , and . Microprocess. Microsystems, (2023)Regional Clock Tree Generation by Abutment in Synchoros VLSI Design., , , and . CoRR, (2019)Enabling area efficient RF ICs through monolithic 3D integration., , , , and . DATE, page 610-613. IEEE, (2017)