( en | de | ru )

 

Disambiguation of "Hormigo, Javier"

Author of the publication

copydeleteadd this publication to your clipboard
On-line Multioperand Addition Based on On-line Full Adders.

, , , and . ASAP, page 322-327. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Javier Manero

Javier Jáurequi

Javier Dreyer

Javier Papa

Javier Arpón

 

Other publications of authors with the same name

Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator., , , , , , and . ICECS, page 419-422. IEEE, (2009)Efficient Floating-Point Givens Rotation Unit., and . CoRR, (2020)Texture segmentation through eigen-analysis of the Pseudo-Wigner distribution., and . Pattern Recognit. Lett., 20 (3): 337-345 (1999)Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest., and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2369-2377 (2016)High-Radix Formats for Enhancing Floating-Point FPGA Implementations., and . Circuits Syst. Signal Process., 41 (3): 1683-1703 (2022)Reproducible Summation Under HUB Format., , and . ARITH, page 38-45. IEEE, (2019)A study of decimal left shifters for binary numbers., , and . Inf. Comput., (2012)Improving fixed-point implementation of QR decomposition by rounding-to-nearest., and . ISCE, page 1-2. IEEE, (2015)Evaluation of Elementary Functions Using Multimedia Features., , , , and . IPDPS, IEEE Computer Society, (2004)Efficient Implementation of Carry-Save Adders in FPGAs., , , , , and . ASAP, page 207-210. IEEE Computer Society, (2009)