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Disambiguation of "Horowitz, Mark"

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Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator.

, , , , and . CoRR, (2020)

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Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Pinchas Horowitz

Charles Horowitz

 

Other publications of authors with the same name

Digital Analog Design: Enabling Mixed-Signal System Validation., , , , and . IEEE Des. Test, 32 (1): 44-52 (2015)Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models., and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 23-33 (2016)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)Towards an explanatory and computational theory of scientific discovery, , , , , and . CoRR, (2009)An Analytical Cache Model., , and . ACM Trans. Comput. Syst., 7 (2): 184-215 (1989)Tiny Tera: a packet switch core., , , , and . IEEE Micro, 17 (1): 26-33 (1997)Rigel: flexible multi-rate image processing hardware., , , , , and . ACM Trans. Graph., 35 (4): 85:1-85:11 (2016)A high-speed, low-power 3D-SRAM architecture., , and . CICC, page 201-204. IEEE, (2008)A Verilog piecewise-linear analog behavior model for mixed-signal validation., and . CICC, page 1-5. IEEE, (2013)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)