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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P. Chen, Y. Mei, M. Strange, R. Daly, C. Donovick, A. Carsello, T. Kong, K. Feng, D. Huff, A. Nayak, R. Setaluri, J. Thomas, N. Bhagdikar, D. Durst, Z. Myers, N. Tsiskaridze, S. Richardson, R. Bahr, K. Fatahalian, P. Hanrahan, C. Barrett, M. Horowitz, C. Torng, F. Kjolstad, and P. Raina. ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)

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Jeff Berens

Ronald Setter

Jeff Bezanson

Cornelia Setter

Dennis Jeffrey

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Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.K. Feng, A. Carsello, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). HCS, page 1-30. IEEE, (2022)Creating an Agile Hardware Design Flow.R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, R. Daly, C. Donovick, D. Durst, K. Fatahalian, K. Feng, P. Hanrahan and 22 other author(s). DAC, page 1-6. IEEE, (2020)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.X. Yang, M. Gao, Q. Liu, J. Setter, J. Pu, A. Nayak, S. Bell, K. Cao, H. Ha, P. Raina and 2 other author(s). ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Compiling Halide Programs to Push-Memory Accelerators.Q. Liu, D. Huff, J. Setter, M. Strange, K. Feng, K. Sreedhar, Z. Wang, K. Zhang, M. Horowitz, P. Raina and 1 other author(s). CoRR, (2021)SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support.X. Wang, S. Chen, J. Setter, and J. Martínez. HPCA, page 121-132. IEEE Computer Society, (2017)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators.Q. Liu, J. Setter, D. Huff, M. Strange, K. Feng, M. Horowitz, P. Raina, and F. Kjolstad. ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P. Chen, Y. Mei and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)

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Disambiguation of "Setter, Jeff"

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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

Please choose a person to relate this publication to

Jeff Berens

Ronald Setter

Jeff Bezanson

Cornelia Setter

Dennis Jeffrey

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Setter, Jeff"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.

Please choose a person to relate this publication to

Jeff Berens

Ronald Setter

Jeff Bezanson

Cornelia Setter

Dennis Jeffrey

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.