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Modelling a 2-D inverse fast cosine transform algorithm on a multistage network, и . Signal Processing, 30 (2): 235--243 (января 1993)TCAM enabled on-chip logic minimization., и . DAC, стр. 678-683. ACM, (2005)Dynamic context management for low power coarse-grained reconfigurable architecture., и . ACM Great Lakes Symposium on VLSI, стр. 33-38. ACM, (2009)Mapping of Neural Network Models Onto Two-Dimensional Processor Arrays., и . Parallel Comput., 22 (10): 1345-1357 (1996)Key Predistribution Schemes for Establishing Pairwise Keys with a Mobile Sink in Sensor Networks., и . IEEE Trans. Parallel Distributed Syst., 22 (1): 176-184 (2011)A reconfigurable computing architecture for semantic information filtering., , , и . IEEE BigData, стр. 212-218. IEEE Computer Society, (2013)Hardware Performance Counters for Embedded Software Anomaly Detection., и . DASC/PiCom/DataCom/CyberSciTech, стр. 528-535. IEEE Computer Society, (2018)Using FPGA implementations for evaluation of internet retransmission-time-out predictors., , и . ECBS, стр. 17:1-17:4. ACM, (2017)Secure Data Collection Scheme in Wireless Sensor Network with Mobile Sink., и . NCA, стр. 332-340. IEEE Computer Society, (2008)A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems., , и . ICCD, стр. 179-185. IEEE Computer Society, (2009)