Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.

Y. Ji, H. Goo, J. Lim, S. Lee, S. Lee, T. Uemura, J. Park, S. Han, S. Shin, J. Lee, Y. Song, K. Lee, H. Shin, S. Hwang, B. Seo, Y. Lee, J. Kim, G. Koh, K. Park, S. Pae, G. Jeong, J. Yoon, and E. Jung. IRPS, page 1-3. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kenji Uemura

Other publications of authors with the same name

Critical charge dependence of correlation of different neutron sources for soft error testing.H. Mori, T. Uemura, H. Matsuyama, S. ichiro Abe, and Y. Watanabe. IRPS, page 2. IEEE, (2015)Impact of package on neutron induced single event upset in 20 nm SRAM.T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto. IRPS, page 9. IEEE, (2015)Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology.H. Jiang, H. Sagong, J. Kim, H. Shim, Y. Kim, J. Park, T. Uemura, Y. Ji, T. Jeong, D. Kwon and 3 other author(s). IRPS, page 1-5. IEEE, (2020)Reliability of Industrial grade Embedded-STT-MRAM.Y. Ji, H. Goo, J. Lim, T. Jeong, T. Uemura, G. Kim, B. Seo, S. Lee, G. Park, J. Jo and 21 other author(s). IRPS, page 1-3. IEEE, (2020)The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server.R. Kan, T. Tanaka, G. Sugizaki, K. Ishizaka, R. Nishiyama, S. Sakabayashi, Y. Koyanagi, R. Iwatsuki, K. Hayasaka, T. Uemura and 5 other author(s). IEEE J. Solid State Circuits, 49 (1): 32-40 (2014)A 10th generation 16-core SPARC64 processor for mission-critical UNIX server.R. Kan, T. Tanaka, G. Sugizaki, R. Nishiyama, S. Sakabayashi, Y. Koyanagi, R. Iwatsuki, K. Hayasaka, T. Uemura, G. Ito and 4 other author(s). ISSCC, page 60-61. IEEE, (2013)Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology.T. Uemura, B. Chung, J. Kim, H. Shim, S. Chung, B. Lee, J. Choi, S. Ohnishi, and K. Machida. IRPS, page 7. IEEE, (2022)Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology.H. Ko, S. Park, J. Ryu, S. Kim, G. Lee, D. Lee, S. Pae, E. Lee, Y. Ji, H. Jiang and 8 other author(s). IRPS, page 1-5. IEEE, (2020)Reliability on EUV Interconnect Technology for 7nm and beyond.T. Jeong, M. Lee, Y. Jo, J. Kim, M. Kim, M. Yeo, J. Kim, H. Choi, J. Kim, Y. Jo and 7 other author(s). IRPS, page 1-4. IEEE, (2020)SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET.T. Uemura, S. Lee, D. Min, I. Moon, S. Lee, and S. Pae. IRPS, page 1-6. IEEE, (2019)

BibSonomy

Disambiguation of "Uemura, Taiki"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.

Please choose a person to relate this publication to

Kenji Uemura

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Uemura, Taiki"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.

Please choose a person to relate this publication to

Kenji Uemura

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology.