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Disambiguation of "Wang, Albert Z."

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A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique.

, , , and . ASICON, page 1-4. IEEE, (2013)

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Z Taufig

Wang Wang

Bence Z Szalai

Leonardo Quevedo Z

Milorad Z Djordjevic

 

Other publications of authors with the same name

A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS., , , , , , and . ISCAS, page 2794-2797. IEEE, (2007)ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress., , , and . ASP-DAC, page 79-82. ACM Press, (2005)Visible Light Communication Cyber-Physical Systems-on- Chip for Smart Cities., , , , , , , and . J. Commun., 14 (12): 1141-1146 (2019)Introduction to the Special Section on the 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.. IEEE J. Solid State Circuits, 49 (9): 1875 (2014)Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (5): 1100-1110 (2011)An optimized UWB correlator design with the consideration of the impacts from the ESD protection devices., , and . Sci. China Inf. Sci., 56 (6): 1-9 (2013)Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 49 (9): 1927-1941 (2014)A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS., , , , , and . IEEE Access, (2020)ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1421-1428 (2004)Integrated stacked-Spiral RF inductor with nanopowder magnetic Core., , , , , , and . J. Circuits Syst. Comput., (2013)