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Disambiguation of "Ramírez, Marco Antonio"

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A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures.

, , , , , and . ACM Trans. Archit. Code Optim., 17 (4): 38:1-38:30 (2020)

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Rafael Ramírez

Rafael Ramírez

Pablo Antonio Rivera Ramirez

Marco Antonio Mirata

Marco Antonio Delpiano

 

Other publications of authors with the same name

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures., , , , , and . CoRR, (2021)A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation., , , , and . ICCD, page 647-653. IEEE Computer Society, (2005)An Academic RISC-V Silicon Implementation Based on Open-Source Components., , , , , , , , , and 24 other author(s). DCIS, page 1-6. IEEE, (2020)A Simple Low-Energy Instruction Wakeup Mechanism., , , , and . ISHPC, volume 2858 of Lecture Notes in Computer Science, page 99-112. Springer, (2003)A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures., , , , , and . ACM Trans. Archit. Code Optim., 17 (4): 38:1-38:30 (2020)Lagarto I - Una plataforma hardware/software de arquitectura de computadoras para la academia e investigación., , , , , and . Res. Comput. Sci., (2017)A partitioned instruction queue to reduce instruction wakeup energy., , , , and . Int. J. High Perform. Comput. Netw., 1 (4): 153-161 (2004)A distributed processor state management architecture for large-window processors., , , , , and . MICRO, page 11-22. IEEE Computer Society, (2008)Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm., , , , and . J. Electron. Test., 31 (4): 361-380 (2015)An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism., , , , , , and . J. Electron. Test., 33 (4): 431-447 (2017)