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Disambiguation of "Gulak, P. Glenn"

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Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders.

, , , and . VLSI Signal Processing, 39 (1-2): 93-111 (2005)

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Samet Gülak

Andreas Glennemeier

Eduardo Glenn Calvo

Alexandra Gulake-Butyra

Glenn Reinhardt

 

Other publications of authors with the same name

(lambda, T) Complexity Measures for VLSI Computations in Constant Chip Area., , , and . IEEE Trans. Computers, 36 (1): 112-117 (1987)An efficient architecture for distributed resampling for high-speed particle filtering., and . ISCAS, IEEE, (2006)Single-filter multi-color CMOS fluorescent contact sensing microsystem., , , , and . ISCAS, page 2393-2396. IEEE, (2012)Reduced complexity symbol detectors with parallel structure for ISI channels., , and . IEEE Trans. Commun., 42 (234): 1661-1671 (1994)A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (2): 327-340 (2013)Multicast contention resolution with single-cycle windowing using content addressable FIFO's., and . IEEE/ACM Trans. Netw., 4 (5): 731-742 (1996)Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression., , and . Data Compression Conference, page 254-263. IEEE Computer Society, (1994)A robust RAM-THP architecture for downlink multiuser MISO transmission with user scheduling., and . SiPS, page 334-339. IEEE, (2011)A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder., , and . ICASSP, page 3173-3176. IEEE, (2008)A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (5): 419-434 (1998)