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Disambiguation of "Chen, Liang-Gee"

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Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator.

, , , and . ISCAS, page 2083-2086. IEEE, (2010)

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Liang Chen

Liang Chen

Liang Chen

Liang-chi Chen

Yen-liang Chen

 

Other publications of authors with the same name

A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications., , , , , , , , , and 2 other author(s). ISSCC, page 154-155. IEEE, (2009)An efficient architecture for two-dimensional discrete wavelet transform., and . IEEE Trans. Circuits Syst. Video Techn., 11 (4): 536-545 (2001)Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000., , , and . IEEE Trans. Circuits Syst. Video Techn., 13 (3): 219-230 (2003)A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm., and . IEEE Trans. Circuits Syst. Video Techn., 8 (2): 124-127 (1998)Reconfigurable architecture for video applications., , , , and . SoCC, page 21-24. IEEE, (2007)CDSP: an application-specific digital signal processor for third generation wireless communications., , and . IEEE Trans. Consumer Electronics, 47 (3): 672-677 (2001)Low-power multi-processor system architecture design for universal biomedical signal processing., , and . ISCAS, page 857-860. IEEE, (2013)Level C+ data reuse scheme for motion estimation with corresponding coding orders., , , and . IEEE Trans. Circuits Syst. Video Techn., 16 (4): 553-558 (2006)Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements., , and . IEEE Trans. Circuits Syst. Video Techn., 15 (9): 1156-1169 (2005)Scalable module-based architecture for MPEG-4 BMA motion estimation., , , and . ISCAS (2), page 245-248. IEEE, (2001)