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Disambiguation of "Kimura, Shinji"

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Synthesis of parallel prefix adders considering switching activities.

, , and . ICCD, page 404-409. IEEE Computer Society, (2008)

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T Kimura

Shuji Kimura

Shinji Koiwa

Shinji Maeda

Naoji Kimura

 

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Multi-Operand Adder Synthesis Targeting FPGAs., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2579-2586 (2011)Issue Mechanism for Embedded Simultaneous Multithreading Processor., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (4): 1092-1100 (2008)Foreword.. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 2961 (2009)14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications., , , , , , , , , and 1 other author(s). ISSCC, page 266-268. IEEE, (2016)Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression., , , and . ISCAS, page 1-5. IEEE, (2018)A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor., , , , and . IEICE Trans. Electron., 100-C (3): 223-231 (2017)Framework for Parallel Prefix Adder Synthesis Considering Switching Activities., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 996-1004 (2006)Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity., , and . ASP-DAC, page 190-195. IEEE, (2018)Transition-based coverage estimation for symbolic model checking., , , and . ASP-DAC, page 1-6. IEEE, (2006)