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Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis., , , , and . DSD, page 267-273. IEEE Computer Society, (2008)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , and . DSD, page 308-315. IEEE Computer Society, (2002)Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Enhanced gradient-based motion vector coprocessor., , , , , and . FPL, page 687-690. IEEE, (2009)Bit-level scheduling of heterogeneous behavioural specifications., , and . ICCAD, page 602-608. ACM / IEEE Computer Society, (2002)Power optimization in heterogenous datapaths., , , , and . DATE, page 1400-1405. IEEE, (2011)Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits., , , and . DSD, page 464-471. IEEE Computer Society, (2008)High-level synthesis of multiple-precision circuitsindependent of data-objects length., , and . DAC, page 612-615. ACM, (2002)A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths., , , , and . Integr., 46 (2): 119-130 (2013)High-Level Allocation to Minimize Internal Hardware Wastage., , and . DATE, page 10264-10269. IEEE Computer Society, (2003)