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Disambiguation of "Molina, María C."

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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.

, , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)

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María Isabel Grasa Molina

Jose Maria Gonzalez Molina

Maria C Schmitt

Maria C Schmitt

Carlos Molina

 

Other publications of authors with the same name

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis., , , , and . DSD, page 267-273. IEEE Computer Society, (2008)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , and . DSD, page 308-315. IEEE Computer Society, (2002)Arrival time aware scheduling to minimize clock cycle length., , , and . ASP-DAC, page 1018-1021. ACM Press, (2005)Performance-driven scheduling of behavioural specifications., , , and . Integr., 42 (3): 294-303 (2009)Multiple-Precision Circuits Allocation Independent of Data-Objects Length., , and . DATE, page 909-913. IEEE Computer Society, (2002)Pre-synthesis optimization of multiplications to improve circuit performance., , , and . DATE, page 1306-1311. European Design and Automation Association, Leuven, Belgium, (2006)Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (1): 60-73 (2009)High-level synthesis of multiple-precision circuitsindependent of data-objects length., , and . DAC, page 612-615. ACM, (2002)A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths., , , , and . Integr., 46 (2): 119-130 (2013)