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Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware.

, , , , , and . ISCA, page 575-586. ACM, (2017)

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Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , and . ISCAS, page 1-4. IEEE, (2017)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , and . DAC, page 64:1-64:6. ACM, (2016)Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , and . ISCAS, page 2541-2544. IEEE, (2013)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation., , , and . ASP-DAC, page 312-317. IEEE, (2017)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs., , , , , , , , , and . NVMSA, page 1-6. IEEE, (2017)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors., , , and . J. Parallel Distributed Comput., 74 (9): 2818-2830 (2014)Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1895-1908 (2016)Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3085-3098 (2015)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system., , , , , and . Sci. China Inf. Sci., 57 (8): 1-14 (2014)